Memory devices that include so-called power-down modes have been developed in an attempt to reduce the amount of current drawn by the device when not actively being used. An example of such a memory device 10 is shown is FIG. 1. Memory device 10 includes a data input path in which data signals 12 received at input pins of the device are conditioned (e.g., converted to appropriate internal levels, usually CMOS) in data buffers 14. In response to internal write signals 16 (which may be generated in response to appropriate external control signals), the data signals arc driven, using bus drivers 18, onto selected bit lines 20a and 20b. The bits lines 20a and 20b are associated with a particular column of memory cells 22, the column corresponding to the particular bit line pair being driven. When memory device 10 is not being actively written to or read from, the bit lines are equalized through the use of static and/or dynamic bit line pull up circuits 24, as is well known in the art. The read path circuitry of memory device 10 is not shown in detail, however, it may include conventional elements such as sense amplifiers and appropriate interface circuitry to provide signals from the memory cells to the output pins of the device.
Also shown in FIG. 1 is a portion of the address path circuitry for memory device 10. Address signals 26 are conditioned in associated address input buffers 28. The address signals may be provided to appropriate decoding circuitry, such as the row predecoders 30, in order to access selected rows (wordlines) of memory device 10. Further details regarding the row decoding circuitry is not shown in order not to obscure the diagram.
In addition to driving the word-line decoding circuitry, signals from the address input buffers 28 are provided to individual address transition detection (ATD) signal generators 32 to produce individual ATD signals 34. The individual ATD signals 34 provide an indication that an address switching event has occurred at the input of the memory device. Such address switching events are generally associated with read and write operations, and the associated ATD pulses are often used in memory devices to perform functions such as bit line equalization. For example, prior to any read, bit lines of the memory device must be properly equalized so as not to provide initial false readings to the associated sense amplifiers. The individual ATD signals 34 may be combined at an ATD combination stage 36 to produce a global ATD signal 38 which may be used for such functions. The ATD signal 38, together with appropriate block decoding and write detect signals 40 and 42, respectively, may be provided to the control circuitry 44 to control the dynamic bitline pullups, to enable/disable the sense amplifiers, as appropriate, and/or to allow write access to the bit lines from the data write bus drivers 18. Further details regarding such circuitry may be found in U.S. Pat. No. 5,825,715, incorporated herein by reference.
In addition to using the individual ATD signals 34, the ATD combination block 36 relies on a signal provided by a chip enable input buffer 46 of memory device 10. Chip enable input buffer 46 receives a chip enable (e.g., CE, active low) signal 48, which is typically provided to an input pin of the memory device 10. In response, input buffer 46 provides an output signal 50, which may be delayed by an appropriate period (.tau..sub.2) through a delay block 52 before being passed to the ATD combination block 36. In this way appropriate timing for the global ATD signal 38 may be provided, simultaneously with its activation during standby, usually for bitline equalization purposes.
Chip enable input buffer 46 also provides a fast power-up signal 54 to thc address input buffers 28. This fast power-up signal 54 is used to indicate that the memory device 10 is about to enter a power-down mode, in which the outputs of the address input buffers 28 are brought to a predetermined logic state, or is powering-up from such a power-down mode. In some cases, the fast power-up signal 54 may also be provided to the row predecoders 30, for example through an appropriate delay (.tau..sub.1) 56.
In operation, when memory device 10 is placed in a power-down mode, indicated by the memory device being deselected (i.e., CE at a high logic level), the address input buffers 28 are forced to a predetermined state so that in case the address is changed externally (e.g., as may be the case where a different memory device is selected). the input buffers do not toggle, and thus the power consumption is kept lower. When the address buffers are placed in such a state, a corresponding address (e.g., address 00 . . . 00) might be active within memory device 10. As a result, when the memory device is powered-up and a new address is selected, an ATD pulse will be generated.
The generation of such an ATD pulse presents a problem in that the normal device access time will be pushed out. For example, consider that a normal access time (Taa) is a function of the normal ATD pulse width. However, at power-up the ATD signal itself is not produced until the fast power-up signal 54 is received from the chip enable input buffer 46. In other words, the access time due to the chip enable function (Tace) is a function of the delay within the chip enable input buffer 46 plus the regular access time Taa. Thus, Tace becomes a limiting factor for the speed of memory device 10 and, generally, this not an acceptable condition.
Although others have recognized this access timing problem associated with memory devices that allow for power-down modes, the solutions that have been proposed to date are generally unacceptable. For example, Shinohara et al., proposed a chip select speed-up circuit that accelerated the trailing edge of an ATD signal within a memory device. See, Shinohara et al., A 45-ns 256 k CMOS Static RAM with a Tri-Level Wordline, IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, pp. 929-34, at 931 (October 1985). Although the acceleration of the trailing edge of the ATD signal may improve access time somewhat, it does not eliminate the problem posed by the Tace push-out. Indeed, because the solution proposed by Shinohara et al., does not eliminate the ATD signal generated at power-up, one can expect the Tace condition to always remain a limiting factor for memory devices incorporating such a solution.
A second solution that has been proposed by Flannagan et al., uses what appears to be rather complex circuitry in an effort to correlate various internal signals within the memory device. See Flannagan et al., IEEE Journal of Solid State Circuits Vol. SC-21, No. 5, pp. 692-703, at 697-98 (October 1986). In their design, Flannagan et al. proposed inhibiting the ATD signal which would be otherwise generated at power-up but failed to discuss any details regarding how this inhibiting function is performed. In addition, it appears that the solution proposed by Flannagan et al. may suffer from push-out penalties of its own if the first access after the stand-by mode is made to the same column of memory cells as was addressed by the predetermined power-down address, especially where data of the opposite logic state is to be read.
Moreover, given the logic circuitry shown by Flannagan et al. (see FIG. 10 at p. 697), it does not appear that an ATD signal will be inhibited only if a proper bit line equalization has been assured during the power-down state. To elaborate, consider that the Flannagan design uses separate ATD and chip enable signal paths that are ultimately combined in a summation OR-type gate. This design dictates that the block (no label is provided for this block) in the ATD signal path determines the duration of the ATD pulse. Also, the minimum duration of the stand-by equalization pulse cannot help but be determined by the block (again unlabeled) in the chip enable signal path. At the very least, such a design would make it difficult to assure proper bit line equalization during stand-by.
Accordingly, what is needed is a solution for the Tace condition described above that overcomes the failings of previously posed solutions therefor.